The present invention relates to a channel device of a computer system, and more particularly to a channel system suitable for a long distance data transfer between a processor and I/O devices, wherein a channel device is divided into a central channel device and a remote channel device with respect to its function, and the two devices are connected via a serial transfer line such as an optical fiber.
Data chaining, channel command and command chaining are described in the specification of U.S. Pat. No. 4,272,815 entitled "CHANNEL CONTROL SYSTEM FOR CONTROLLING DATA TRANSFER THROUGH A PLURALITY OF CHANNELS WITH PRIORITY ASSIGNMENT".
As shown in FIG. 1, long distance data transfer between a central processing unit 1 and an I/O device 4 has been realized heretofore by interposing interface converters 2 and 3 between I/O interfaces 5 and 7 respectively of the central processing unit 1 and the I/O device 4. In FIG. 1, the interface converter 2 converts parallel signals from the I/O interface 5 into serial signals and sends them via a serial interface line 6 such as an optical fiber to the interface converter 3 which in turn converts the serial signals into I/O parallel interface signals and sends them via the I/O interface 7 to the I/O device 4. Signals from the I/O device 4 are sent to the central processing unit 1 in an opposite manner to the above.
An example of data transfer sequence from the central processing unit 1 to the I/O device 4 according to a conventional method is shown in FIG. 2. Particularly, when a request signal 701 is outputted from the I/O device 4, it is transferred via the interface converters 2 and 3 to the central processing unit 1. In accordance with a transfer command in a program, the central processing unit 1 can send an acknowledge signal 702 and data 703. These operations (701 to 703) are repeated so many times as necessary after a request 701 to transfer required data.
With this method, it takes however a long time to carry out the sequence for the request and acknowledge signals and data transfer if the number of I/O devices communicating with the central processing unit is large, because the speed of an I/O device is low. Thus, performance of the system is degraded.
To solve this problem, a system providing buffer memories in the interface converters 2 and 3 is known as in Japanese Patent Kokai (Laid-Open) No. 57-212534. An analysis of this system was made by the present inventor to explain the problems included in data transfer sequence between the central processing unit and I/O devices, which sequence is shown in FIG. 3. Particularly, before a request signal is outputted from the I/O device 4, a sequence for inputting a predetermined amount of data 803 to the buffer storage of the interface converter 2 is preliminarily repeated after a request signal 801 and an acknowledge signal 802 are exchanged between the central processing unit and the interface converter 2. The inputted data is sent via the serial interface line 6 to the interface converter 3 and stored in the buffer storage thereof. The stored data 806 as well as an acknowledge signal 805 is sent to the I/O device 4 when a request signal 804 is outputted from the I/O device 4. In this manner, it is possible to shorten the time required for transfer of request and acknowledge signals and data between the central processing unit 1 and the I/O device 4, thus preventing degrading the system performance in spite of a long distance data transfer.
However, there are some problems with the system shown in FIG. 3: in a case where the I/O device 4 stops requesting data although data still remains in the buffer memories of the interface converters 2 and 3, since the central processing unit 1 judges that all transferred data has already been sent to the I/O device 4, the program is not supplied with a correct information that the remaining data is not actually sent. Also, during a succeeding data chaining transfer from different storage locations to the buffer storage of the interface converter 2, there may occur such a case that the I/O device completes the data transfer processing for the preceding command and the last address during data transfer for the preceding channel command word can not be informed to the program, although the central processing unit is going to execute the processing for a current command. This is an essential problem of this system since it is constructed such that the central processing unit operates without considering the operation of the interface converters interposed between the I/O interfaces.